
PIC18F66K80 FAMILY
DS39977F-page 166
2010-2012 Microchip Technology Inc.
REGISTER 10-18: IPR5: PERIPHERAL INTERRUPT PRIORITY REGISTER 5
R/W-1
IRXIP
WAKIP
ERRIP
TXB2IP
TXB1IP
TXB0IP
RXB1IP
RXB0IP/
FIFOFIE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
IRXIP:
Invalid Message Received Interrupt Priority bits
1
= High priority
0
= Low priority
bit 6
WAKIP:
Bus Wake-up Activity Interrupt Priority bit
1
= High priority
0
= Low priority
bit 5
ERRIP:
CAN Bus Error Interrupt Priority bit
1
= High priority
0
= Low priority
bit 4
TXB2IP:
Transmit Buffer 2 Interrupt Priority bit
1
= High priority
0
= Low priority
bit 3
TXB1IP:
Transmit Buffer 1 Interrupt Priority bit
1
= High priority
0
= Low priority
bit 2
TXB0IP:
Transmit Buffer 0 Interrupt Priority bit
1
= High priority
0
= Low priority
bit 1
RXB1IP:
Receive Buffer 1 Interrupt Priority bit
Mode 0:
1
= High priority for Receive Buffer 1
0
= Low priority for Receive Buffer 1
Modes 1 and 2:
1
= High priority for received messages
0
= Low priority for received messages
bit 0
RXB0IP/FIFOFIP:
Receive Buffer 0 Interrupt Priority bit
Mode 0:
1
= High priority for Receive Buffer 0
0
= Low priority for Receive Buffer 0
Mode 1:
Unimplemented:
Read as ‘0’
Mode 2:
FIFOFIE:
FIFO Full Interrupt Flag bit
1
= High priority
0
= Low priority